EDAToolsCafe, the Worlds #1 EDA Web Portal.
Search:
HP Invent
  Home | Companies | Downloads | Demos | News | Jobs | Resources | Books & Courses |  ItZnewz  | |  CaféTalk 
  Check Mail | Free Email | Submit Material | Universities | Designers Corner | Events | e-Contact | Membership | Fun Stuff | Weather | Advertise | e-Catalog Signup >> Site Tour <<
 Browse eCatalog:  Free subscription to EDA Daily News
eCatalogAsic & ICPCBFPGADesign Services
Email: 

News: Subscribe to NewsAgent |  Company News |  News Jump |  Post News
  EDA Company News
Research Center EDAToolsCafe Research Center  

Printer Friendly Version

Verplex Places Verification Library in Public Domain

MILPITAS, Calif.--(BUSINESS WIRE)--Nov. 20, 2000--A verification library that provides detailed logic debugging capability was placed in the public domain today by Verplex(TM) Systems, Inc., the electronic design automation (EDA) company known for its formal verification software.

Additionally, it is launching the Open Verification Library initiative to promote its use and encourage the library's acceptance as a de facto industry standard.

Verplex is offering the library to provide seamless interoperability between simulation and formal verification, eliminating the learning curve and accelerating the acceptance of formal RTL design verification software. The library was designed using the Verilog Hardware Description Language (HDL) and works with any Verilog HDL-based or mixed-language simulator. It enables users to find bugs deeply embedded in the design, where chip- or system-level test vectors may have little control or may not be sufficiently long enough to propagate errors to an observable output.

Early formal register transfer level (RTL) design verification software had a steep learning curve because of complex, proprietary specification languages. Formal specifications written in these languages are often difficult to understand and debug.

Simulation users, however, are familiar with embedded event or assertion monitoring mechanisms to trap and report design errors.

The verification library is a plug-in supplement to monitoring mechanisms, extending their applicability into more detailed error detection and reporting. Designers choose the appropriate monitor from the library and place it in (or connect it to) the suspected area of the design where the bug may occur. If a test vector triggers the monitor during simulation, an error will be reported to the user.

The monitor-based library verification technique was proposed in a textbook titled, ``Principles of Verifiable RTL Design,'' by Harry Foster and Lionel Bening of Hewlett-Packard Company (NYSE: HWP) in Richardson, Texas, and published by Kluwer Academic Publishers. It is currently used throughout Hewlett-Packard in Richardson.

``We are grateful to Harry and Lionel for sharing this common sense approach,'' remarks C. Michael Chang, president and chief executive officer of Verplex, noting that it was conceived and matured by the user community. ``It yields immediate benefit to simulation users and provides a seamless and effortless path to formal verification.''

Multiple companies have lent endorsement and support. They include: Axis Systems, Inc.; Chronology Corporation; Co-Design Automation, Inc.; Denali Software, Inc.; Hewlett-Packard; Magma Design Automation, Inc.; Novas Software, Inc.; and Ricoh Company, Ltd.

  • (In related news, Verplex announced today the immediate availability of BlackTie(TM) functional checker which fully supports the Open Verification Library. The same monitors written for simulation can be verified using BlackTie. When verifying monitors with BlackTie, test vectors are not required, coverage is exhaustive and the diagnosis is automatic.)

    The verification library can be downloaded at no charge from the Web Site located at: http://www.verificationlib.org. The site features a download area, submission area, full documentation and a discussion group. Visitors to the site are encouraged to contribute their own customized monitors and enhance existing ones.

    For more information, contact Dino Caporossi, director of marketing at Verplex. He can be reached at (301) 390-2718 or via email at dino@verplex.com.

    About Verplex

    Verplex Systems Inc. is an electronic design automation (EDA) company focused on delivering the highest speed, highest capacity and easiest to use formal verification products for complex system-on-chip (SOC) design. Founded in 1997, it is privately held and funded by leading venture capital firms. Corporate headquarters is located at 300 Montague Expressway, Suite 100, Milpitas, Calif. 95035. Telephone: (408) 586-0300. Facsimile: (408) 586-0230. Email: info@verplex.com. Online information is found at its Web Site: http://www.verplex.com.

    Verplex, BlackTie and Tuxedo-LEC are trademarks of Verplex Systems Inc. All other companies and products referenced herein are trademarks or registered trademarks of their respective holders.


    Contact:
         Verplex Systems, Inc.
         Nanette Collins
         (617) 437-1822
         nanette@nvc.com

  • Learn More about Aldec-HDL 4.0XE
    Copyright 2000, Internet Business Systems, Inc.
    1-888-44-WEB-44 --- marketing@ibsystems.com
    Support
    Phone Support